1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an auto-program circuit in the nonvolatile semiconductor memory device.
2. Description of the Related Arts
A memory cell array with NAND structured cells has a plurality of NAND cell units arranged in a matrix with columns and rows. FIG. 9 is an equivalent circuit diagram showing a part of the memory cell array with conventional NAND structured cells. Referring to the figure, each of the NAND cell units NU1 to NUm has a first selection transistor 120 with its drain connected to the corresponding bit line and a second selection transistor 121 with its source connected to a common source line CSL. The drain-source channels of memory cell transistors M1 to M8 (hereinafter referred to as "memory cells") are serially connected between a source of the first selection transistor 120 and a drain of the second selection transistor 121. The gates of the first selection transistors 120, the control gates of the memory cells M1 to M8 and the gates of the second selection transistors 121 are connected to a first selection line SL1, word lines WL1 to WL8 and a second selection line SL2, respectively. The first and second selection transistors 120 and 121 and the memory cells M1 to M8 are formed in the P type well formed on the main surface of a semiconductor substrate. The source-drain common region between the source of the first selection transistor 120 and the drain of the memory cell M1, the source-drain common regions of the memory cells M1 to M8, and the drain-source common region between the drain of the second selection transistor 121 and the source of the memory cell M8 are formed in the P type well. A floating gate made of polysilicon is formed on each channel of the memory cells M1 to M8 through a tunnel oxide layer, and a floating gate made of polysilicon or of metal silicide with high melting point is formed thereon through an intermediate insulating layer. The drain regions of the first selection transistors 120 formed in the P type well are respectively connected to the corresponding bit lines made of metal silicide with high melting point or metal through openings, the source regions of the second selection transistors 121 formed in the P type well are connected to the common source line CSL made of the metal silicide with high melting point or metal. The erase operation for the memory cells is performed before programming, i.e., writing data.
The erase operation for the memory cells is performed by applying erase voltage of about 20 V to the P type well region and reference voltage, i.e., ground voltage to the word lines WL1 to WL8. With the electrons stored in the floating gates being emitted to the P type well region through the tunnel oxide layer, the memory cells are changed to enhancement mode transistors. It can be assumed that the erased memory cells store the data "1".
The programming operation for the memory cells connected to the selected word line, i.e., the writing operation of the data "0" is performed by applying program voltage of about 18 V to the selected word line and the reference voltage, i.e., the ground voltage Vss to the sources and drains of the memory cells in which the data "0" is written. Then, the floating gates of the memory cells to be programmed accumulate the electrons thorough the tunnel oxide layers, and these memory cells are changed to the depletion mode transistors.
After programming, the program verification operation is performed to verify whether or not the selected memory cells are successfully programmed to have a predetermined constant threshold voltage value. These erase, program and program verification techniques are disclosed in the Korean Patent Publication No. 94-18870 published Aug. 19, 1994 and assigned to the present inventor.
As the capacitance of the EEPROM has become highly integrated, the size of the memory cell, such as the width and thickness of the gate oxide layer and the width and length of the channel region, has been reduced. However, variance of the manufacturing process can not secure the uniformity of the width and thickness of the gate oxide layer, intermediate insulating layer and channel region. This makes the threshold voltage values of the programmed memory cells unequal. If at least one of the programmed memory cells does not reach a desired threshold voltage, error data is read out. In order to solve such a problem, a program verification device has been proposed for verifying whether or not the selected memory cells are successfully programmed. For example, such a program verification technique is disclosed in the aforementioned Korean Patent Publication No. 94-18870. However, as the reprogram operation is performed after the program verification operation with a program voltage of constant level, the threshold voltages of the programmed memory cells are still unequal. The variance of the circumstance conditions such as a power supply voltage or an operating temperature may deteriorate the reliability of the EEPROM.